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? semiconductor components industries, llc, 2006 december, 2006 ? rev. 2 1 publication order number: NCP1271/d NCP1271 soft?skip mode standby pwm controller with adjustable skip level and external latch the NCP1271 represents a new, pin to pin compatible, generation of the successful 7?pin current mode ncp12xx product series. the controller allows for excellent stand by power consumption by use of its adjustable soft?skip mode and integrated high voltage startup fet. this proprietary soft?skip also dramatically reduces the risk of acoustic noise. this allows the use of inexpensive transformers and capacitors in the clamping network. internal frequency jittering, ramp compensation, timer?based fault detection and a latch input make this controller an excellent candidate for converters where ruggedness and component cost are the key constraints. features ? fixed?frequency current?mode operation with ramp compensation and skip cycle in standby condition ? timer?based fault protection for improved overload detection ? ?soft?skip mode? technique for optimal noise control in standby ? internal high?voltage startup current source for lossless startup ? 5% current limit accuracy over the full temperature range ? adjustable skip level ? internal latch for easy implementation of overvoltage and overtemperature protection ? frequency jittering for softened emi signature ? +500 ma/?800 ma peak current drive capability ? sub?100 mw standby power can be achieved ? pin?to?pin compatible with the existing ncp120x series ? this is a pb?free device typical applications ? ac?dc adapters for notebooks, lcd monitors ? offline battery chargers ? consumer electronic appliances stb, dvd, dvdr *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. pin connections http://onsemi.com marking diagrams (top view) 1271x alyw x = a or b a= 65 khz b= 100 khz a = assembly location l = wafer lot y = year w = work week = pb?free package 1 8 (note: microdot may be in either location) skip/latch fb cs gnd 1 2 3 4 hv v cc drv 8 6 5 soic?7 d suffix case 751u soic?7 see detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet. ordering information
NCP1271 http://onsemi.com 2 figure 1. typical application circuit skip/latch fb cs gnd NCP1271 voltage + ? ac input output r ramp latch input* emi filter r skip hv vcc drv * * optional maximum ratings (notes 1 and 2) rating symbol value unit v cc pin (pin 6) maximum voltage range maximum current v max i max ?0.3 to +20 100 v ma skip/latch, fb, cs pin (pins 1?3) maximum voltage range maximum current v max i max ?0.3 to +10 100 v ma drv pin (pin 5) maximum voltage range maximum current v max i max ?0.3 to +20 ?800 to +500 v ma hv pin (pin 8) maximum voltage range maximum current v max i max ?0.3 to +500 100 v ma power dissipation and thermal characteristics thermal resistance, junction?to?air, so?7, low conductivity pcb (note 3) thermal resistance, junction?to?lead, so?7, low conductivity pcb thermal resistance, junction?to?air, so?7, high conductivity pcb (note 4) thermal resistance, junction?to?lead, so?7, high conductivity pcb r ja r jl r ja r jl 177 75 136 69 c/w c/w c/w c/w operating junction temperature range t j ?40 to +125 c maximum storage temperature range t stg ?60 to +125 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device contains esd protection and exceeds the following tests: pins 1?6: human body model 2000 v per mil?std?883, method 3015 machine model method 150 v (on pins 5 and 6) and 200 v (all other pins) pin 8 is the hv startup of the device and is rated to the maximum rating of the part, or 500 v this device contains latchup protection and exceeds 100 ma per jedec standard jesd78. 2. guaranteed by design, not tested. 3. as mounted on a 40x40x1.5 mm fr4 substrate with a single layer of 80 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec 51 low conductivity test pcb. test conditions were under natural convection or zero air flow. 4. as mounted on a 40x40x1.5 mm fr4 substrate with a single layer of 650 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec 51 high conductivity test pcb. test conditions were under natural convection or zero air flow.
NCP1271 http://onsemi.com 3 figure 2. functional block diagram ? leb skip/ latch cs fb 7.5% jittering 65, 100 khz oscillator 130ms delay hv s r drv gnd pwm skip or 4.8 v 8 v max duty r s = 80% 180 ns 0 & + ? + ? + ? + soft?skip 8 2 3 4 1 6 5 v ss v fb latch?off, reset when vcc < 4v jittered ramp current source i v short circuit fault 12.6/ 5.8 v 9.1 v turn off uvlo ? + ? + turn on internal bias 4.1 ma when vcc > 0.6 v driver: +500 ma / ?800 ma 10v disable soft skip skip & double hiccup s q 10v 10v 20v v cs v cc v cc 0 100ua 0.2 ma when vcc < 0.6 v soft start/ soft?skip management ? tld + soft start 2.85 v 1 / 3 13 us filter 1 0 skip r skip 4 ms/ 300 us r cs r ramp (1v max) 16.7k 75.3k v / 3 fb v pwm v fb q r q 2 counter v skip = r skip * i skip or v skip = 1.2 v when pin 1 is opened 1 pin function description pin no. symbol function description 1 skip/latch skip adjust or latchoff a resistor to ground provides the adjustable standby skip level. additionally, if this pin is pulled higher than 8.0 v (typical), the controller latches off the drive. 2 fb feedback an optocoupler collector pulls this pin low during regulation. if this voltage is less than the skip pin voltage, then the driver is pulled low and soft?skip mode is activated. if this pin is open (>3 v) for more than 130 ms, then the controller is placed in a fault mode. 3 cs current sense this pin senses the primary current for pwm regulation. the maximum primary current is limited to 1.0 v / r cs where r cs is the current sense resistor . additionally, a ramp resistor r ramp between the current sense node and this pin sets the compensation ramp for improved stability. 4 gnd ic ground ? 5 drv driver output the NCP1271?s powerful output is capable of driving the gates of large qg mosfets. 6 v cc supply v oltage this is the positive supply of the device. the operating range is between 10 v (min) and 20 v (max) with a uvlo start threshold 12.6 v (typ). 8 hv high v oltage this pin provides (1) lossless startup sequence (2) double hiccup fault mode (3) memory for latch?off shutdown and (4) device protection if v cc is shorted to gnd.
NCP1271 http://onsemi.com 4 electrical characteristics (for typical values t j = 25 c, for min/max values, t j = ?40 c to +125 c, v cc = 14 v, hv = open, skip = open, fb = 2 v, cs = ground, drv = 1 nf, unless otherwise noted.) characteristic pin symbol min typ max unit oscillator oscillation frequency (65 khz version, t j = 25 c) oscillation frequency (65 khz version, t j = ?40 to + 85 c) oscillation frequency (65 khz version, t j = ?40 to + 125 c) oscillation frequency (100 khz version, t j = 25 c) oscillation frequency (100 khz version, t j = ?40 to +85 c) oscillation frequency (100 khz version, t j = ?40 to +125 c) 5 f osc 61.75 58 55 95 89 85 65 65 65 100 100 100 68.25 69 69 105 107 107 khz oscillator modulation swing, in percentage of f osc 5 ? ? 7.5 ? % oscillator modulation swing period 5 ? ? 6.0 ? ms maximum duty cycle (v cs = 0 v, v fb = 2.0 v) 5 d max 75 80 85 % gate drive gate drive resistance output high (v cc = 14 v, drv = 300 to gnd) output low (v cc = 14 v, drv = 1.0 v) 5 r oh r ol 6.0 2.0 11 6.0 20 12 rise time from 10% to 90% (drv = 1.0 nf to gnd) 5 t r ? 30 ? ns fall time from 90% to 10% (drv = 1.0 nf to gnd) 5 t f ? 20 ? ns current sense maximum current threshold 3 i limit 0.95 1.0 1.05 v soft?start duration ? t ss ? 4.0 ? ms soft?skip duration ? t sk ? 300 ? s leading edge blanking duration 3 t leb 100 180 330 ns propagation delay (drv =1.0 nf to gnd) ? ? ? 50 150 ns ramp current source peak 3 i ramp(h) ? 100 ? a ramp current source valley 3 i ramp(l) ? 0 ? a skip default standby skip threshold (pin 1 = open) 2 v skip ? 1.2 ? v skip current (pin 1 = 0 v, t j = 25 c) 1 i skip 26 43 56 a skip level reset (note 5) 1 v skip?reset 5.0 5.7 6.5 v transient load detection level to disable soft?skip mode 2 v tld 2.6 2.85 3.15 v external latch latch protection threshold 1 v latch 7.1 8.0 8.7 v latch threshold margin (v latch?m = v cc(off) ? v latch ) 1 v latch?m 0.6 1.2 ? v noise filtering duration 1 ? ? 13 ? s propagation delay (drv = 1.0 nf to gnd) 1 t latch ? 100 ? ns short?circuit fault protection time for validating short?circuit fault condition 2 t protect ? 130 ? ms 5. please refer to figure 39 for detailed description. 6. guaranteed by design.
NCP1271 http://onsemi.com 5 electrical characteristics (continued) (for typical values t j = 25 c, for min/max values, t j = ?40 c to +125 c, v cc = 14 v, hv = open, skip = open, fb = 2 v, cs = ground, drv = 1 nf, unless otherwise noted.) characteristic pin symbol min typ max unit startup current source high?v oltage current source inhibit voltage (i cc = 200 a, hv = 50 v) inhibit current (v cc = 0 v, hv = 50 v) startup (v cc = v cc(on) ? 0.2 v, hv = 50 v) leakage (v cc = 14 v, hv = 500 v) 6 6 6 8 v inhibit i inhibit i hv i hv?leak 190 80 3.0 10 600 200 4.1 25 800 350 6.0 50 mv a ma a minimum startup voltage (v cc = v cc(on) ? 0.2 v, i cc = 0.5 ma) 8 v hv(min) ? 20 28 v supply section v cc regulation startup threshold, v cc increasing minimum operating voltage after t urn?on v cc operating hysteresis undervoltage lockout threshold voltage, v cc decreasing logic reset level (v cc(latch) ?v cc(reset) > 1.0 v) (note 7) 6 v cc(on) v cc(off) v cc(on) ? v cc(off) v cc(latch) v cc(reset) 11.2 8.2 3.0 5.0 ? 12.6 9.1 3.6 5.8 4.0 13.8 10 4.2 6.5 ? v v v v v v cc supply current operating (v cc = 14 v, 1.0 nf load, v fb = 2.0 v, 65 khz v ersion) operating (v cc = 14 v, 1.0 nf load, v fb = 2.0 v, 100 khz v ersion) output stays low (v cc = 14 v, v fb = 0 v) latchoff phase (v cc = 7.0 v, v fb = 2.0 v) 6 i cc1 i cc1 i cc2 i cc3 ? ? ? ? 2.3 3.1 1.3 500 3.0 3.5 2.0 720 ma ma ma a 7. guaranteed by design. typical characteristics figure 3. oscillation frequency vs. temperature figure 4. maximum duty cycle vs. temperature temperature ( c) temperature ( c) 125 100 75 50 25 0 ?50 50 60 70 80 90 100 110 125 100 75 50 25 0 ?50 75 76 77 78 79 80 81 oscillation frequency (khz) maximum duty cycle (%) ?25 ?25 82 83 84 85 100 khz 65 khz
NCP1271 http://onsemi.com 6 typical characteristics figure 5. output gate drive resistance vs. temperature figure 6. current li mit vs. temperature figure 7. soft?start duration vs. temperature figure 8. leading edge blanking time vs. temperature temperature ( c) temperature ( c) 125 100 75 50 25 0 ?50 0 2 4 6 8 10 12 5 100 75 50 25 0 ?50 0.94 0.96 0.98 1.0 1.04 output gate drive resistance ( ) current limit (v) figure 9. default skip level vs. temperature figure 10. skip pin current vs. temperature temperature ( c) 1 25 100 75 50 25 0 ?50 0 100 200 300 leading edge blanking time (ns) temperature ( c) 125 100 75 50 25 0 ?50 1.00 1.10 1.20 1.30 1.40 default skip level (v) 50 150 250 350 ?25 ?25 ?25 ?25 12 14 16 r oh r ol 1.02 temperature ( c) 125 100 75 50 25 0 ?50 0 2 4 6 soft?start duration (ms) 1 3 5 8 ?25 7 temperature ( c) 12 5 100 75 50 25 0 ?50 35 36 37 38 39 40 41 skip pin current ( a) ?25 42 43 44 45
NCP1271 http://onsemi.com 7 typical characteristics figure 11. skip level reset threshold vs. temperature figure 12. transient load detection level vs. temperature temperature ( c) 125 100 75 50 25 0 ?50 5.5 5.6 5.7 5.8 5.9 6.0 skip level reset threshold (v) figure 13. latch protection level vs. temperature figure 14. fault validation time vs. temperature temperature ( c) temperature ( c) 1 25 100 75 50 25 0 ?50 2.5 2.6 2.7 2.8 2.9 3.0 125 100 75 50 25 0 ?50 7.5 7.6 7.7 7.8 7.9 transient load detect level (v ) latch protection level (v) figure 15. startup inhibit voltage vs. temperature figure 16. startup inhibit current vs. temperature temperature ( c) 125 100 75 50 25 0 ?50 0 0.2 0.4 0.6 0.8 1.0 startup inhibit voltage (v) temperature ( c) 12 5 100 75 50 25 0 ?50 0 50 100 150 200 250 startup inhibit current ( a) 300 0.1 0.3 0.5 0.7 0.9 ?25 ?25 ?25 ?25 ?25 8.0 8.1 8.2 8.3 8.4 8.5 v cc = 0 v temperature ( c) 12 5 100 75 50 25 0 ?50 100 105 110 115 120 fault v alidation time (ms) ?25 125 130 135 140 145 150
NCP1271 http://onsemi.com 8 typical characteristics figure 17. high v oltage startup current vs. temperature figure 18. startup current vs. v cc voltage temperature ( c) v cc , supply voltage (v) 125 100 75 50 25 0 ?50 3.5 3.6 3.7 3.8 3.9 4.0 4.1 1 2 10 8 6 4 0 0 1 2 3 4 5 6 startup current (ma) startup current (ma) figure 19. startup leakage current vs. temperature figure 20. minimum startup voltage vs. temperature temperature ( c) temperature ( c) 1 25 100 75 50 25 0 ?50 15 17 19 21 23 25 125 100 75 50 25 0 ?50 0 2 4 6 8 minimum startup voltage (v) supply volt age threshold (v) figure 21. supply voltage thresholds vs. temperature temperature ( c) 12 5 100 75 50 25 0 ?50 0 0.5 1.0 1.5 2.0 2.5 supply current (ma) ?25 2 ?25 ?25 ?25 v cc(reset) v cc(on) 4.2 4.3 4.4 4.5 16 18 20 22 24 10 12 14 v cc(off) v cc(latch) v cc = v cc(on) ? 0.2 v 3.0 3.5 figure 22. supply currents vs. temperature temperature ( c) 125 100 75 50 25 0 ?50 0 5 10 15 20 25 30 startup leakage current ( a) ?25 35 40 125 c ?40 c 25 c i cc1 (100 khz) i cc2 i cc3 i cc1 (65 khz)
NCP1271 http://onsemi.com 9 operating description introduction the NCP1271 represents a new generation of the fixed?frequency pwm current?mode flyback controllers from on semiconductor. the device features integrated high?voltage startup and excellent standby performance. the proprietary soft?skip mode achieves extremely low?standby power consumption while keeping power supply acoustic noise to a minimum. the key features of the NCP1271 are as follows: ? timer?based fault detection: in the event that an abnormally large load is applied to the output for more than 130 ms, the controller will safely shut the application down. this allows accurate overload (ol) or short?circuit (sc) detection which is not dependent on the auxiliary winding. ? soft?skip mode: this proprietary feature of the NCP1271 minimizes the standby low?frequency acoustic noise by ramping the peak current envelope whenever skip is activated. ? adjustable skip threshold: this feature allows the power level at which the application enters skip to be fully adjusted. thus, the standby power for various applications can be optimized. the default skip level is 1.2 v (40% of the maximum peak current) . ? 500 v high?voltage startup capability: this ac?dc application friendly feature eliminates the need for an external startup biasing circuit, minimizes the standby power loss, and saves printed circuit board (pcb) space. ? dual high?voltage startup?current levels: the NCP1271 uniquely provides the ability to reduce the startup current supply when vcc is low. this prevents damage if vcc is ever shorted to ground. after vcc rises above approximately 600 mv, the startup current increases to its full value and rapidly charges the vcc capacitor. ? latched protection: the NCP1271 provides a pin, which if pulled high, places the part in a latched off mode. therefore, overvoltage (ovp) and overtemperature (otp) protection can be easily implemented. a noise filter is provided on this function to reduce the chances of falsely triggering the latch. the latch is released when vcc is cycled below 4 v. ? non?latched protection/ shutdown option: by pulling the feedback pin below the skip threshold level, a non?latching shutdown mode can be easily implemented. ? 4.0 ms soft?start: the soft start feature slowly ramps up the drive duty cycle at startup. this forces the primary current to also ramp up slowly and dramatically reduces the stress on power components during startup. ? current?mode operation: the NCP1271 uses current?mode control which provides better transient response than voltage?mode control. current?mode control also inherently limits the cycle?by?cycle primary current. ? compensation ramp: a drawback of current?mode regulation is that the circuit may become unstable when the operating duty cycle is too high. the NCP1271 offers an adjustable compensation ramp to solve this instability. ? 80% maximum duty cycle protection: this feature limits the maximum on time of the drive to protect the power mosfet from being continuously on. ? frequency jittering: frequency jittering softens the emi signature by spreading out peak energy within a band +/? 7.5% from the center frequency. ? switching frequency options: the NCP1271 is available in either 65 khz or 100 khz fixed frequency options. depending on the application, the designer can pick the right device to help reduce magnetic switching loss or improve the emi signature before reaching the 150 khz starting point for more restrictive emi test limits. NCP1271 operating conditions there are 5 possible operating conditions for the NCP1271: 1. normal operation ? when v cc is above v cc(off) (9.1 v typical) and the feedback pin voltage (v fb ) is within the normal operation range (i.e.,v fb < 3.0 v), the NCP1271 operates as a fixed?frequency current?mode pwm controller. 2. standby operation (or skip?cycle operation) when the load current drops, the compensation network responds by reducing the primary peak current. when the peak current reaches the skip peak current level, the NCP1271 enters soft?skip operation to reduce the power consumption. this soft?skip feature offers a modified peak current envelope and hence also reduces the risk of audible noise. in the event of a sudden load increase, the transient load detector (tld) disables soft?skip and applies maximum power to bring the output into regulation as fast as possible. 3. fault operation ? when no feedback signal is received for 130 ms or when v cc drops below v cc(off) (9.1 v typical), the NCP1271 recognizes it as a fault condition. in this fault mode, the vcc voltage is forced to go through two cycles of slowly discharging and charging. this is known as a ?double hiccup.? the double hiccup insures that ample time is allowed between restarts to prevent overheating of the power devices. if the fault is
NCP1271 http://onsemi.com 10 cleared after the double hiccup, then the application restarts. if not, then the process is repeated. 4. latched shutdown ? when the skip/latch pin (pin 1) voltage is pulled above 8.0 v for more than 13 s, the NCP1271 goes into latchoff shutdown. the output is held low and v cc stays in hiccup mode until the latch is reset. the reset can only occur if vcc is allowed to fall below v cc(reset) (4.0 v typical). this is generally accomplished by unplugging the main input ac source. 5. non?latched shutdown ? if the fb pin is pulled below the skip level, then the device will enter a non?latched shutdown mode. this mode disables the driver, but the controller automatically recovers when the pulldown on fb is released. alternatively, vcc can also be pulled low (below 190 mv) to shutdown the controller. this has the added benefit of placing the part into a low current consumption mode for improved power savings. biasing the controller during startup, the vcc bias voltage is supplied by the hv pin (pin 8). this pin is capable of supporting up to 500 v, so it can be connected directly to the bulk capacitor. internally, the pin connects to a current source which rapidly charges v cc to its v cc(on) threshold. after this level is reached, the controller turns on and the transformer auxiliary winding delivers the bias supply voltage to v cc. the startup fet is then turned off, allowing the standby power loss to be minimized. this in?chip startup circuit minimizes the number of external components and printed circuit board (pcb) area. it also provides much lower power dissipation and faster startup times when compared to using startup resistors to v cc . the auxiliary winding needs to be designed to supply a voltage above the v cc(off) level but below the maximum v cc level of 20 v. for added protection, the NCP1271 also include a dual startup mode. initially, when v cc is below the inhibit voltage v inhibit (600 mv typical), the startup current source is small (200 ua typical). the current goes higher (4.1 ma typical) when v cc goes above v inhibit . this behavior is illustrated in figure 23. the dual startup feature protects the device by limiting the maximum power dissipation when the v cc pin (pin 6) is accidentally grounded. this slightly increases the total time to charge v cc , but it is generally not noticeable. figure 23. startup current at various v cc levels v v cc(on) cc 4.1 ma 200 ua startup current 0.6 v v cc(latch) v cc double hiccup mode figure 24 illustrates the block diagram of the startup circuit. an undervoltage lockout (uvlo) comparator monitors the v cc supply voltage. if v cc falls below v cc(off) , then the controller enters ?double hiccup mode.? figure 24. v cc management vcc hv 8 6 12.6/ 5.8 v 9.1 v turn off uvlo ? + ? + turn on internal bias & double hiccup q r 20v 4.1 ma when vcc > 0.6 v 200 ua when vcc < 0.6 v 10?to?20v biasing voltage (available after startup) 2 counter s v bulk during double hiccup operation, the vcc level falls to v cc(latch) (5.8 v typical). at this point, the startup fet is turned back on and charges v cc to v cc(on) (12.6 v typical). v cc then slowly collapses back to the v cc(latch) level. this cycle is repeated twice to minimize power dissipation in
NCP1271 http://onsemi.com 11 external components during a fault event. after the second cycle, the controller tries to restart the application. if the restart is not successful, then the process is repeated. during this mode, v cc never drops below the 4 v latch reset level. therefore, latched faults will not be cleared unless the application is unplugged from the ac line (i.e., v bulk discharges). figure 25 shows a timing diagram of the v cc double hiccup operation. note that at each restart attempt, a soft start is issued to minimize stress. figure 25. v cc double hiccup operation in a fault condition 5.8 v 12.6 v 9.1 v d t startup time cc supply voltage, v time drain current, i switching is missing in every two v cc hiccup cycles featuring a ?double?hiccup? v cc capacitor as stated earlier, the NCP1271 enters a fault condition when the feedback pin is open (i.e. fb is greater than 3 v) for 130 ms or v cc drops below v cc(off) (9.1 v typical). therefore, to take advantage of these features, the v cc capacitor needs to be sized so that operation can be maintained in the absence of the auxiliary winding for at least 130 ms. the controller typically consumes 2.3 ma at a 65 khz frequency with a 1 nf switch gate capacitance. therefore, to ensure at least 130 ms of operation, equation 1 can be used to calculate that at least an 85 f capacitor would be necessary. t startup c vcc v i cc1 85 f (12.6 v?9.1 v) 2.3 ma 130 ms (eq. 1) if the 130 ms timer feature will not be used, then the capacitance value needs to at least be large enough for the output to charge up to a point where the auxiliary winding can supply v cc . figure 26 describes different startup scenarios with different v cc capacitor values. if the v cc cap is too small, the application fails to start because the bias supply voltage cannot be established before v cc is reduced to the v cc(off) level. figure 26. different startup scenarios of the circuits with different v cc capacitors time v v out cc time v cc out v 9.1 v 12.6 v 5.8 v 9.1 v 12.6 v t startup 0.6 v 0.6 v output waveforms with a large enough v cc capacitor output waveforms with too small of a v cc capacitor desired level of v out it is highly recommended that the v cc capacitor be as close as possible to the v cc and ground pins of the product to reduce switching noise. a small bypass capacitor on this pin is also recommended. if the switching noise is large enough, it could potentially cause v cc to go below v cc(off) and force a restart of the controller. it is also recommended to have a margin between the winding bias voltage and v cc(off) so that all possible transient swings of the auxiliary winding are allowed. in standby mode, the v cc voltage swing can be higher due to the low?frequency skip?cycle operation. the v cc capacitor also affects this swing. figure 27 illustrates the possible swings. figure 27. timing diagram of standby condition v fb d 9.1 v cc skip time supply voltage, v time feedback pin voltage, v time drain current, i
NCP1271 http://onsemi.com 12 soft?start operation figures 28 and 29 show how the soft?start feature is included in the pulse?width modulation (pwm) comparator. when the NCP1271 starts up, a soft?start voltage v ss begins at 0 v. v ss increases gradually from 0 v to 1.0 v in 4.0 ms and stays at 1.0 v afterward. this voltage v ss is compared with the divided?by?3 feedback pin voltage (v fb /3). the lesser of v ss and (v fb /3) becomes the modulation voltage v pwm in the pwm duty cycle generation. initially, (v fb /3) is above 1.0 v because the output voltage is low. as a result, v pwm is limited by the soft start function and slowly ramps up the duty cycle (and therefore the primary current) for the initial 4.0 ms. this provides a greatly reduced stress on the power devices during startup. figure 28. v pwm is the lesser of v ss and (v fb /3) 0 1 ? + v ss v / 3 fb v pwm figure 29. soft?start (time = 0 at v cc = v cc(on) ) time time time 1 v 4 ms 1 v 1 v 4 ms time must be less than130 ms to prevent fault condition time 4 ms feedback pin voltage divided?by?3, v fb /3 pulse width modulation voltage, v pwm drain current, i d soft?start voltage, v ss current?mode pulse?width modulation the NCP1271 uses a current?mode fixed?frequency pwm with internal ramp compensation. a pair of current sense resistors r cs and r ramp sense the flyback drain current i d . as the drain current ramps up through the inductor and current sense resistor , a corresponding voltage ramp is placed on the cs pin (pin 3). this voltage ranges from very low to as high as the modulation voltage v pwm (maximum of 1.0 v) before turning the drive off. if the internal current ramp is ignored (i.e., r ramp 0) then the maximum possible drain current i d(max) is shown in equation 2. this sets the primary current limit on a cycle by cycle basis. i d(max) 1v r cs (eq. 2) figure 30. current?mode implementation leb cs pwm output 180ns + ? 3 v bulk r ramp (1v max. signal) v pwm q s v cs clock 1 0 r cs i d 80% max duty i ramp r figure 31. current?mode timing diagram pwm output v pwm cs clock v the timing diagram of the pwm is in figure 31. an internal clock turns the drive output (pin 5) high in each switching cycle. the drive output goes low when the cs (pin 3) voltage v cs intersects with the modulation voltage v pwm . this generates the pulse width (or duty cycle). the maximum duty cycle is limited to 80% (typically) in the output rs latch.
NCP1271 http://onsemi.com 13 ramp compensation ramp compensation is a known mean to cure subharmonic oscillations. these oscillations take place at half the switching frequency and occur only during continuous conduction mode (ccm) with a duty?cycle greater than 50%. to lower the current loop gain, one usually injects between 50 and 75% of the inductor down slope. the NCP1271 generates an internal current ramp that is synchronized with the clock. this current ramp is then routed to the cs pin. figures 32 and 33 depict how the ramp is generated and utilized. ramp compensation is simply formed by placing a resistor, r ramp , between the cs pin and the sense resistor. figure 32. internal ramp current source ramp current, i 0 100ua time 80% of period ramp 100% of period figure 33. inserting a resistor in series with the current sense information brings ramp compensation clock current ramp oscillator drive cs r ramp r sense 100 a peak for the NCP1271, the current ramp features a swing of 100 a. over a 65 khz frequency with an 80% max duty cycle, that corresponds to an 8.1 a/ s ramp. for a typical flyback design, let?s assume that the primary inductance (lp) is 350 h, the smps output is 19 v, the vf of the output diode is 1 v and the np:ns ratio is 10:1. the off time primary current slope is given by: (eq. 3) (vout vf) np ns lp 571 v mh 571 ma s when projected over an rsense of 0.1 (for example), this becomes or 57 mv/ s. if we select 75% of the downslope as the required amount of ramp compensation, then we shall inject 43 mv/ s. therefore, r ramp is simply equal to: (eq. 4) r ramp 43 mv s 8.1 a s 5.3 k it is recommended that the value of r ramp be limited to less then 10 k . values larger than this will begin to limit the effective duty cycle of the controller and may result in reduced transient response. frequency jittering frequency jittering is a method used to soften the emi signature by spreading the energy in the vicinity of the main switching component. the NCP1271 switching frequency ranges from +7.5% to ?7.5% of the switching frequency in a linear ramp with a typical period of 6 ms. figure 34 demonstrates how the oscillation frequency changes. figure 34. frequency jittering (the values are for the 100 khz frequency option) time oscillator frequency 92.5 khz 107.5 khz 100 khz 6 ms fault detection figure 35 details the timer?based fault detection circuitry. when an overload (or short circuit) event occurs, the output voltage collapses and the optocoupler does not conduct current. this opens the fb pin (pin 2) and v fb is internally pulled higher than 3.0 v. since (v fb /3) is greater than 1 v, the controller activates an error flag and starts a 130 ms timer. if the output recovers during this time, the timer is reset and the device continues to operate normally. however, if the fault lasts for more than 130 ms, then the driver turns off and the device enters the v cc double hiccup mode discussed earlier. at the end of the double hiccup, the controller tries to restart the application. figure 35. block diagram of timer?based fault detection softstart fb 130ms delay 1v max fault & ? + 2 v ss v fb disable drv v fb 3 4.8v
NCP1271 http://onsemi.com 14 besides the timer?based fault detection, the NCP1271 also enters fault condition when v cc drops below v cc (off ) (9.1 v typical). the device will again enter a double hiccup mode and try to restart the application. operation in standby condition during standby operation, or when the output has a light load, the duty cycle on the controller can become very small. at this point, a significant portion of the power dissipation is related to the power mosfet switching on and off. to reduce this power dissipation, the NCP1271 ?skips? pulses when the fb level (i.e. duty cycle) drops too low. the level that this occurs at is completely adjustable by setting a resistor on pin 1. by discontinuing pulses, the output voltage slowly drops and the fb voltage rises. when the fb voltage rises above the v skip level, the drive is turned back on. however, to minimize the risk of acoustic noise, when the drive turns back on the duty cycle of its pulses are also ramped up. this is similar to the soft start function, except the period of the soft?skip operation is only 300 s instead of 4.0 ms for the soft start function. this feature produces a timing diagram shown in figure 36. figure 36. soft?skip operation v fb i d skip soft skip skip duty cycle skip peak current, %ics skip , is the percentage of the maximum peak current at which the controller enters skip mode. ics skip can be any value from 0 to 100% as defined by equation 5. however, the higher that %ics skip is, the greater the drain current when skip is entered. this increases the risk of acoustic noise. conversely, the lower that %ics skip is the larger the percentage of energy is expended turning the switch on and off. therefore it is important to adjust %ics skip to the optimal level for a given application. %ics skip v skip 3v 100% (eq. 5) skip adjustment by default, when the skip/latch pin (pin 1) is opened, the skip level is 1.2 v (v skip = 1.2 v). this corresponds to a 40% ics skip (%ics skip = 1.2 v / 3.0 v 100% = 40%). therefore, the controller will enter skip mode when the peak current is less than 40% of the maximum peak current. however, this level can be externally adjusted by placing a resistor r skip between skip/latch pin (pin 1) and ground (pin 4). the level will change according to equation 6. v skip r skip i skip (eq. 6) to operate in skip cycle mode, v skip must be between 0 v and 3.0 v. therefore, r skip must be within the levels given in table 1. table 1. skip resistor r skip range for d max = 80% and i skip = 43 a %ics skip v skip or v pin1 r skip comment 0% 0 v 0 never skips. 12% 0.375 v 8.7 k ? 25% 0.75 v 17.4 k ? 40% 1.2 v 28 k ? 50% 1.5 v 34.8 k ? 100% 3.0 v 70 k always skips.
NCP1271 http://onsemi.com 15 recover from standby in the event that a large load is encountered during skip cycle operation, the circuit automatically disables the normal soft?skip procedure and delivers maximum power to the load (figure 37). this feature, the transient load detector (tld), is initiated anytime a skip event is exited and the fb pin is greater than 2.85 v, as would be the case for a sudden increase in output load. figure 37. transient response from standby v v fb i d skip v tld load current maximum current available when tld level is hit output voltage 300 s max external latchoff shutdown when the skip/latch input (pin 1) is pulled higher than v latch (8.0 v typical), the drive output is latched off until v cc drops below v cc(reset) (4.0 v typical ). if vbulk stays above approximately 30 vdc, then the hv fet ensure that v cc remains above v cc(latch) (5.8 v typical ). therefore, the controller is reset by unplugging the power supply from the wall and allowing v bulk to discharge. figure 38 illustrates the timing diagram of v cc in the latchoff condition. figure 38. latchoff v cc timing diagram 5.8 v 12.6 v startup current source is charging the v cc capacitor startup current source is off when v cc is 12.6 v startup current source turns on when v cc reaches 5.8 v cc figure 39 defines the different voltage regions of the skip/latch pin (pin 1) operation. 1. when the voltage is above v latch (7.1 v min, 8.7 v max), the circuit is in latchoff and all drive pulses are disabled until v cc cycles below 4.0 v (typical). 2. when the voltage is between v skip?reset (5.0 v min, 6.5 v max) and v latch , the pin is considered to be opened. the skip level v skip is restored to the default 1.2 v. 3. when the voltage is between about 3.0 v and v skip?reset , the v skip level is above the normal operating range of the feedback pin. therefore, the output does not switch. 4. when the voltage is between 0 v and 3.0 v, the v skip is within the operating range of the feedback pin. then the voltage on this pin sets the skip level as explained earlier. figure 39. NCP1271 pin 1 operating regions output is latched off here. adjustable v range. 0 v (no skip) 3.0 v (always skip) v pin1 8v (v ) 10 v (max limit) output always low (skipped) here. 5.7 v (v ) pin 1 considered to be opened. skip?reset latch skip v skip is reset to default level 1.2 v. the external latch feature allows the circuit designers to implement different kinds of latching protection. the NCP1271 applications note (and8242/d) details several simple circuits to implement overtemperature protection (otp) and overvoltage protection (ovp). in order to prevent unexpected latchoff due to noise, it is very important to put a noise decoupling capacitor near pin 1 to increase the noise immunity. it is also recommended to always have a resistor from pin 1 to gnd. this further reduces the risk of premature latchoff. also note that if the additional latch?off circuitry has leakage, it will modify the skip adjust setup. external non?latched shutdown figure 40 illustrates the feedback (pin 2) operation. an external non?latched shutdown can be easily implemented by simply pulling fb below the skip level. this is an inherent feature from the standby skip operation. hence, it allows the designer to implement additional non?latched shutdown protection. the device can also be shutdown by pulling the v cc pin to gnd (<190 mv). in addition to shutting off the output, this method also places the part into a low current consumption state.
NCP1271 http://onsemi.com 16 figure 40. NCP1271 operation threshold fault operation when staying in this region longer than 130 ms pwm operation non?latched shutdown 3 v v fb 0 v v skip figure 41. non?latchoff shutdown 1 2 3 4 8 6 5 NCP1271 off opto coupler output drive the output stage of the device is designed to directly drive a power mosfet. it is capable of up to +500 ma and ?800 ma peak drive currents and has a typical rise and fall time of 30 ns and 20 ns with a 1.0 nf load. this allows the NCP1271 to drive a high?current power mosfet directly for medium?high power application. noise decoupling capacitors there are three pins in the NCP1271 that may need external decoupling capacitors. 1. skip/latch pin (pin 1) ? if the voltage on this pin is above 8.0 v, then the circuit enters latchoff. hence, a decoupling capacitor on this pin is essential for improved noise immunity. additionally, a resistor should always be placed from this pin to gnd to prevent noise from causing the pin 1 level to exceed the latchoff level. 2. feedback pin (pin 2) ? the fb pin is a high impedance point and is very easily polluted in a noisy environment. this could effect the circuit operation. 3. v cc pin (pin 6) ? the circuit maintains normal operation when v cc is above v cc(off) (9.1 v typical). but, if v cc drops below v cc(off) because of switching noise, then the circuit can incorrectly recognize it as a fault condition. hence, it is important to locate the v cc capacitor or an additional decoupling capacitor as close as possible to the device.
NCP1271 http://onsemi.com 17 figure 42. 57 w example circuit using NCP1271 ic1 NCP1271a + ? 85 to 265 vac 19 v / 3 a common mode choke d8 mbr3100 r1 100k / 2w r5 15.8k e3506?a d6 mra4005t3 1n5406 x 4 d7 murs160 r7 511 d9 1n5358b (22v@50ma) ic2 sfh615aa?x007 r9 1.69k c3 82uf / 400v ic4 tl431 q1 spp06n80c3 0.2 / 1w d5 mmsz914 c4 100uf r2 10 d10 mzp4746a (18v) r10 8.87k c9 2200 uf c10 2200 uf r6 10 ic3 sfh615aa?x007 c5 10 nf flyback transformer : cooper ctx22?17179 lp = 180uh, leakage 2.5uh max np : ns : naux = 30 : 6 : 5 hi?pot 3600vac for 1 sec, primary to secondary hi?pot 8500vac for 1 sec, winding to core c12 0.15 uf c7 1.2 nf c6 1.2 nf c2 0.1 uf t1 c1 0.1 uf d1 ? d4 r12 2.37k r11 15.8k r13 25 c11 1nf/ 1000v r8 r3 200 fuse 2a c13 100uf c14 100pf figure 42 shows a typical application circuit using the NCP1271. the standby power consumption of the circuit is 83 mw with 230 v ac input. the details of the application circuit are described in application note and8242/d. the efficiency of the circuit at light load up to full load is shown in figure 43. figure 43. efficiency of the NCP1271 demo board at nominal line voltages p out (w) 60 50 40 30 20 0 60 65 70 75 80 85 90 efficiency (%) 10 95 230 vac 120 vac
NCP1271 http://onsemi.com 18 ordering information device frequency package shipping ? NCP1271d65r2g 65khz soic?7 (pb?free) 2500 t ape & reel NCP1271d100r2g 100 khz soic?7 (pb?free) 2500 tape & reel ?for information on tape and reel specifications, including part orientation and tap e sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d.
NCP1271 http://onsemi.com 19 package dimensions soic?7 d suffix case 751u?01 issue c seating plane 1 4 5 8 r j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b are datums and t is a datum surface. 4. dimension a and b do not include mold protrusion. 5. maximum mold protrusion 0.15 (0.006) per side. s d h c dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?a? ?b? g m b m 0.25 (0.010) ?t? b m 0.25 (0.010) t s a s m 7 pl on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. NCP1271/d soft?skip is a trademark of semiconductor components industries, llc (scillc). the product described herein (NCP1271), may be covered by the following u.s. patents: 6,271,735, 6,362,067, 6,385,060, 6,597,22 1, 6,633,193. there may be other patents pending. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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